1. Field of the Invention
The invention relates to a semiconductor device and fabrication method thereof, and more particularly, to a vertical gate-all-around field-effect transistor and fabrication method thereof.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
Nevertheless, as dimension of the device progresses into 10 nm or even more advanced 7 nm node, the current FinFET architecture gradually becomes insufficient for overcoming current physical limitations. Hence, how to create a device that is capable of maintaining adequate performance under small scale has becoming an important task in this field.